Pre-workshops & Tutorials

Integration Session

4  December 2018, 9:00-12:00
The integration workshop focuses on testing products in MicroTCA.4 environment. DESY – together with partners – will provide the testing environment consisting of MicroTCA.4 Chassis, MCHs, Power Supplies and Rear Transition Modules. Participants have the possibility to verify the operation of their products within this environment. Due to the present developers and experts, problems will be identified and investigated.

The number of places are limited. Please register as soon as possible at the registration form.
The integration sessions will be held in building 3, seminar room BAH1 (ground floor).

 

Tutorials

R & S Tutorial

Topic:  Signal integrity, power integrity and EMI are key concerns for modern embedded designs that include high-speed interfaces. DDR memory interfaces, USB interfaces and PCIe are typical high-speed busses, which can be found in such applications. This talk highlights key aspects that need to be considered when implementing such interfaces and presents methods and tools that are available for debugging such designs.

Presenter: Johannes Ganzert, Application Engineer Oscilloscopes, Rohde & Schwarz, München

Date: Tuesday, 4 December 2018 10:30-12:00
Venue: CFEL, SR I-III


MicroTCA.4 for beginners

Date: Tuesday, 4 December 2018 13:30-15:00
Venue: CFEL, SR I-III

Introduction to ChimeraTK

Date: Tuesday, 4 December 2018 13:30-15:00
Venue: CFEL, SR I-III

Timing in MTCA

Date: Tuesday, 4 December 2018 15:00-17:00
Venue: CFEL, SR I-III

Topic: Presentation of the MRF timing system, White Rabbit timing system, XFEL timing system

Presenter; Kay Rehlich, Jukka Pietarinen, Pilar Gil

Direct Memory Access

Topic: The objective of this tutorial session is to build a simple data acquisition system, in which the data is moved from an external device though an FPGA over PCIe into a CPU memory. The data will be there made available to user applications. We will use DAMC-TCK7 (and its Board Support Package) and a MicroTCA crate as a starting point. Then we will add a couple of Xilinx IP blocks and use Xilinx Linux driver to interface with FPGA modules to get to our final goal: having the data available in Python.

Presenter: Jan Marjanovic, MicroTCA Technology Lab

Date: Tuesday, 4 December 2018 15:00-17:00
Venue: CFEL, SR I-III